A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration

A scaling-friendly and energy-efficient 0-1 MASH ΔΣ ADC is proposed in this work. An 8b SAR is used as the 1st stage for coarse quantization. A ring VCO is used as the 2nd stage for fine quantization. The proposed ADC uses digital background calibration to track VCO gain variation across PVT. A 40nm CMOS prototype achieves a Walden FoM of 18.5 fJ/conv-step while operating from 1.1V supply. Introduction With technology scaling, traditional voltage-domain ADCs face severe challenges due to reduction in transistor intrinsic gain and supply voltage. This has brought to the fore timedomain (TD) quantizers which can leverage technology scaling to build high performance ADCs. Ring VCO is widely used as a TD ADC due to its highly digital nature and simplicity of design [1]-[6]. It also provides an intrinsic 1st-order noise shaping. However, the VCO's frequency tuning gain is nonlinear and highly sensitive to PVT variations, which significantly undermines the ADC accuracy and robustness. In addition, FoMs of existing VCO-based ADCs are around 100fJ/ step [1]-[6], which presents a scope for improvement. This work presents a scaling-friendly and energy-efficient 01 MASH ΔΣ ADC. It combines a coarse SAR with a fine VCO. The VCO is effective at quantizing small voltages in TD. Since the VCO only sees a small SAR residue, the VCO nonlinearity is greatly suppressed and does not need any correction. The PVT variation of the VCO tuning gain can still cause SAR quantization noise leakage, degrading SNDR. To address this issue, a simple, low-power, and fast-convergence digital background calibration technique is developed. It enables the precise tracking of the VCO gain and high ADC linearity. A prototype in 40nm CMOS achieves 74.3 dB SNDR with a BW of 2MHz while consuming only 350μW. Proposed SAR-VCO 0-1 MASH ΔΣ ADC Fig. 1 shows the architecture of the proposed ADC. During Φ1, the input is sampled across the bottom-plates of the DAC array. During Φ2, the sampled input is quantized by the SAR. The residue is fed to a pseudo-differential dual-VCO at Φ3. The VCO performs phase domain integration, and the output is differentiated digitally before being combined with the SAR output to generate the ADC output. To reduce power consumption of the SAR, the bi-directional single-sided switching scheme of [7] has been adopted. The SAR DAC has no redundancy as the VCO can absorb SAR decision errors as long as they are not too large to result in VCO phase overflow. This relaxes the precision requirement of the SAR comparator and saves power. The SAR in turn reduces the VCO swing and obviates the need for any VCO nonlinearity calibration. Fig. 2 shows the circuit diagram of the 2nd stage VCO. Each VCO consists of a 7-stage pseudo-differential ring inverter chain. Although the VCOs quantize the SAR residue Vres only during Φ3, they are not stopped when Φ3 goes low. This is to prevent charge leakage which can corrupt the phase information held by the VCOs. Instead, the VCOs are biased with Icm and run at a fixed frequency during Φ3, which is kept low to save power and reduce phase noise. The digital logic for the 2nd stage runs at the ADC sampling frequency. There is no phase-overflow counter running at high VCO frequency, which significantly lowers the power consumption of the 2nd stage compared to [6]. Fig. 3 shows the ADC model, where G represents the SAR residue voltage attenuation due to parasitic capacitors, KVCO is the VCO tuning gain, Gd is the digital gain, and Rn is a dither. The ADC output can be derived as: = + − 1 − + 1 − Both Rn and SAR conversion errorq1 can be cancelled ifGdmatches the analog inter-stage gainGKVCO. The cancellation ofSAR error allows the use of a low power comparator. The finalquantization noise at the ADC outputdout comes solely fromthe VCO(q2) and is first-order shaped.The VCO gainKVCO is sensitive to PVT variations and cancause mismatch betweenGd andGKVCO, leading to noiseleakage. To solve this issue, an efficient and fast backgroundcalibration technique is developed to precisely track the inter-stage gainGKVCO. An on-chip pseudo-random numbergenerator (PRNG) injects a dither Rn into the SAR DAC.GKVCO is extracted from the difference between thed2 averagesfor Rn =1 and Rn = 0 [8]. The hardware cost of this backgroundcalibration scheme is low. It requires only an extra LSBcapacitor in the DAC, two digital averagers, a MUX, and asubtractor (see Fig. 1). Its convergence speed is very fast. Thisis because the unknown ADC inputVin, which is the primarysource of perturbation in the background calibration loop, issubstantially attenuated by the 1st-stage 8-b SAR [9]. The partind2 that is uncorrelated with Rn is very small.Measurement ResultsThe proposed ADC is implemented in 40nm CMOS. Fig. 4shows the measured spectrum with a 2.2V differential input at500kHz and the sampling frequency of 36MHz. Calibrationimproves the SNDR from 64.5 dB to 74.3 dB at the OSR of 9. The ADC consumes 350μW. Fig. 5 shows the SNDR and SNRsweep versus input amplitude. The ADC has a dynamic rangeof 75.7 dB. The measured histogram ofd2 is shown in Fig. 6.The shift ind2 distributions from Rn=1 to Rn=0 can be clearlyseen, and the difference of the two averages gives the inter-stage gainGKVCO of 1.3. Fig. 7 shows that the proposedbackground calibration has a very fast convergence speed andrequires only 103 samples (or 25μs) to converge. Fig. 8 showsthe die photo. Table I compares the proposed hybrid SAR-VCO ADC with state-of-the-art VCO-based ADCs. It can beseen that this work has a FoM of 18.5 fJ/conv-step whichrepresents a significant improvement over the prior art.References[1] M. Park and M. H. Perrott., ISSCC, pp. 170-172, 2009.[2] G. Taylor and I. Galton, VLSI, pp. 166-167, 2012.[3] K. Reddy, et. al., ISSCC, pp. 152-154, 2012.[4] S. Rao, et. al., VLSI, pp. 68-69, 2013.[5] K. Reddy, et. al., VLSI, pp. 256-257, 2015.[6] A. Sanyal, et. al., CICC, pp. 1-4, 2014.[7] L. Chen, et. al., ESSCIRC, pp. 219-222, 2014.[8] E. Siragusa and I. Galton, JSSC, pp. 2126-2138, 2004.[9] N. Sun, et. al, ESSCIRC, pp. 269-272, 2012. 2016 Symposium on VLSI Circuits Digest of Technical Papers978-1-5090-0635-9/16/$31.00 ©2016 IEEE26 Fig.1. Circuit diagram of the proposed ADC. Fig. 3. Block diagram of the proposed ADC.Fig.2. Circuit diagram showing the 2nd stage VCO. Fig. 4. Measured ADC spectrum with and without calibration. Fig. 5 Measured SNDR and SNR vs input amplitude.Fig. 6. Measuredd2 histogram for Rn=1 and Rn=0. Fig. 7. Measured SNDR convergence curve.Fig. 8. Die photoTable I. Performance summary and comparison. [2] [3] [4] This work Process (nm) 65 90 9040 Power (mW) 11.5 16 4.10.35 Area (mm2) 0.07 0.36 0.160.03 fs (MHz) 1300 600 64036 BW (MHz) 5.1 10 5 3 2 SNDR (dB) 75 78.3 74.7 71.4 74.3 FoMS (dB)1 161 163 165 171 172FoMW (fJ/step)2 246 120 92 18.5 21.3FoMS = SNDR + 10log10(BW/Power)FoMW = Power/(2*BW)/2^ENOB 2016 Symposium on VLSI Circuits Digest of Technical Papers27